U.S. Pat. No. 3,562,709 issued Feb. 9, 1971 to C. V. Srinivasan, is directed to the correction of block errors in transmission of data. In Srinivasan, the matrix used to describe the mathematics for the code arithmetic corresponds to an arrangement similar to that given in the FIG. 1. The principal difference between the Srinivasan matrix and the matrix of FIG. 1, is that the Srinivasan matrix only used one zero on each side of the check bit to separate it from the two arrangements of the data bits. Such an arrangement will work as a block error encoder and a block error detector, locator and corrector. However, this arrangement, suffers from at least two drawbacks. First, under some conditions, errors occurring simultaneously in two blocks can be misinterpreted as a group of errors in a third, totally different, block. Second, under other conditions, errors occurring simultaneously in two blocks can be misinterpreted as a situation where no errors are present at all.
Additional arrangements, where the additional zeros are interspersed within the set of data bits (while preserving the mirror image arrangement of the Srinivasan patent), have been shown to have equally good error detection, location and correction characteristics. Other new arrangements have also been shown to allow the construction of sets of matrices that have some particular total of data bits, such as 2N.
In the previous work described above, the mirror image arrangement of the data bits in a column was used. Also, there was never a case where anything other than a regular arrangement of the check bits into positions in the matrix was described. That is, the check bit in the first column of the matrix was assigned to some element such as the first, the middle or the last and the check bits of subsequent columns were always arranged in a linear fashion going up or down (with a wrap-around included as necessary) for the remaining columns.
U.S. Pat. No. 5,751,740 issued on May 12, 1998 to W. A. Helbig, Sr., corrects the two limitations of the Srinivasan patent by using a matrix arrangement where there are two zeros on each side of the check bit in each column. The Srinivasan patent also shows an identical number of data bits in each column of the matrix while the Helbig '740 patent shows that columns in the matrix may contain differing numbers of data bits with additional zeros used to separate the check bit of a column from the two images of the data bits in the column.
The code matrix shown in FIG. 1 has been constructed according to the teaching of the Helbig '740 patent. In this case, there are five data bits, numbered D1 through D5, that have been placed respectively in the first five element spaces, numbers one through five, of the first column of the matrix. In the next two element spaces, numbers six and seven, are each assigned the value zero. The next element space, number eight, is reserved for the eighth check bit, designated as C8, that will be calculated as the modulo-two sum of the data bits that are put into the eighth element spaces of the other columns of the matrix. In the next two element spaces, numbers nine and ten, are also each assigned the value zero. The last five element spaces, numbered eleven through fifteen, are assigned, in reverse order, the values of the five data bits, numbered D1 through D5, that have been placed respectively in the first five element spaces, numbers one through five, of the first column of the matrix as shown.
Referring still to FIG. 1, the subsequent columns of the matrix are constructed in a similar manner. The difference being, as taught in the Helbig '740 patent, that each subsequent column is circularly shifted by one row from the previous column.
When the placing of the entire group of data bits into the matrix is completed and all of the respective check bits have been calculated and placed into the matrix the information is transmitted. The information is sent by transmitting all of the data bits of the first column, numbered D1 through D5, and the Check Bit, numbered C8, of the first column as a block of bits. This is followed by the transmission of the remaining blocks of data bits and check bit of the other columns of the matrix until all of the information has been sent.
Upon receipt of the information the error syndrome bits are calculated using the information received. If the error syndrome bits indicate that there are one or more errors in one of the blocks of bits received the information is corrected using the error syndrome bits. The Helbig '740 patent contains the equations for determining whether one or more errors are present in a column and how to fix the errors if such exist. However, if errors are found in more than one of the blocks of bits received the errors cannot be corrected.